The test chips were designed and processed in a commercial 0. 6 μm standard CMOS/Bulk process. Device parameters were monitored before and after irradiation with about 9.5 kGy（Si）^60Co γ-rays. Comparisons of the effects with different device sizes and different layout structures were made. The effects of different biasing conditions during irradiation are discussed. The experiment results show that W/L does not change the threshold voltage shift after γ-ray irradiation. Channel length and layout structure enormously influence the leakage between source and drain induced by irradiation.