This work presents a low power, high-throughput JPEG-LS accelerator ASIC featuring an 8-stage pipeline architecture and dual-mode computation reuse technology. The chip is fabricated in 65 nm CMOS and occupies?0.71?mm2?achieving?470?μW?power consumption at 0.8 V supply. With the maximum performance test, this accelerator can achieve a maximum processing speed of 875 fps at a?400×400?image resolution owing to its 8 -stage pipeline architecture.