A novel true time delay (TTD) line with three-loop inductor coupling structure is proposed in this article. This approach effectively reduces the delay cell area and increases the inductance, thereby providing a larger configurable delay range within a limited chip area. By adjusting the electrical length of the inner delay cells while maintaining impedance matching, fine delay resolution and delay flatness are achieved. The proposed true time delay line is implemented in a 65-nm CMOS technology with a frequency bandwidth of 1–11 GHz, providing a maximum delay of 106.7 ps with a delay step of 4.85 ps. The measured group delay rms error is less than 4.6 ps, with less than 2 ps in the frequency range of 2–9 GHz. The maximum delay variation is only 6.1% at each frequency point and remains below 5% for all delay settings above 2 GHz. The loss variation is less than ±0.8 dB for the same switched resistor setting. The compact core area of the circuit is 0.27×1.46 mm2.