This letter proposes an ultracompact attenuator structure consisting mainly of nMOS transistors. The attenuator utilizes the parasitic capacitance of nMOS transistors for phase compensation to reduce the root-mean-square (rms) phase error. The common centroid layout scheme is used to mitigate the impact of process gradients on transistor performance. The proposed attenuator structure, designed and fabricated using a 65-nm CMOS process, features a compact core area of 0.0043 mm2. The fabricated attenuator exhibits a 31.5-dB attenuation range, featuring a 0.5-dB resolution and an insertion loss ranging from 4.3 to 6.4 dB from dc to 20 GHz. The amplitude rms error is within 0.297 dB, and the phase rms error is within 3.21°.