The limitation of reference phase noise (PN) causes problems for the very low-jitter phase-locked loops (PLLs), which is increasingly critical and may be an impediment toward 10 fs jitter. This article presents a multireference PLL (MRPLL) architecture featuring the ability to reduce reference PN by using more reference clocks. The architecture evolution, noise model analysis, and circuit design considerations are presented. Theoretically, the major contributor of reference PN is the reference buffer, including the buffer inside a packaged crystal oscillator (XO) and the buffer ON-chip. Increasing the reference frequency can significantly reduce the PN of the reference buffer. The prototype of the MRPLL is implemented in a 65-nm CMOS process and achieves 16.1 fs jitter.