The fast-developing 5G communication is setting increasingly stringent requirements for on-chip voltage-controlled oscillators (VCOs). On the one hand, the VCOs need to generate an extreme pure spectrum to support complicated modulations, corresponding to a low phase noise (PN). On the other hand, a wider frequency tuning range (FTR) is preferred for various wideband applications. In addition, the flicker noise up-conversion has become a serious issue worsening PN at low offset frequencies, especially at advanced technology nodes. Practice has been made to improve the PN and FTR performance. The VCO in [1] covers a wide FTR of 80.6% through triple modes using standard V DD However, no harmonic shaping technique is used to improve PN, and it also suffers from the sacrificed tank's Q because of the asymmetry topology. In [2], the author uses circular topology inductors to obtain a high Q for a 22.4-to-26.8GHz VCO. A ?138dBc/Hz low PN at 10MHz offset is achieved. However, the common-mode (CM) harmonic manipulation is absent, resulting in a 1.06MHz 1/f 3 corner frequency. Nevertheless, a tail-less NMOS-only structure may face reliability issues under standard V DD The VCO in [3] reaches low PN with low 1/f 3 corner frequencies using 2nd harmonic shaping while maintaining high-Q circular topology. However, the oscillator doesn't feature 3 rd harmonic shaping and multi-mode operation, covering only an FTR of 17.6%.