Memory consumes large portion of power in today's digital signal processors (DSPs). This paper proposes a memory partitioning method for power reduction. Based on dynamic execution profile of application-specific programs running on a given DSP, a multi-banked on-chip memory architecture well fitted to the application is developed. With a practical and maneuverable process, this method can achieve a near-optimum solution for low power. Experimental result shows that it can save about 50% of the power at best with little area overhead.