The ripple suppression performance of low-dropout regulators (LDOs) is crucial when cascading them after a DC/DC converter to achieve high power efficiency [1], [2]. Analog LDOs (A-LDOs) and Hybrid LDOs (H-LDOs) achieve decent ripple suppression but suffer from heavy analog components, leading to design complexity and scalability issues [3]–[5]. Recently, a digital LDO (D-LDO) employing a time-domain digital-pre-distortion (DPD) technique was introduced [6], which provides a digital scheme for ripple suppression. However, the ripple suppression performance severely degrades when the ripple period is a non-integer multiple of the clock period. To address this issue, this paper introduces a period multiplication technique based on an optimal integer approximation scheme to minimize the period residual when conducting ripple cancelation. The measurement results indicate that the proposed D-LDO achieves equally decent ripple suppression performance in various decimal situations of T RIPPLE /T CLK . Moreover, this work proposes a transient-response-enhancement architecture based on a threshold-adjustable inverter to compensate for the output-voltage undershoot/overshoot.