The design of a low-power 13bit, 107sample/s pipelined analog -to-digital converter (ADC) in 0.6μm CMOS technology was described. The capacitor error averaging technique was used to achieve the 13bit precision, with circuit techniques such as operational amplifier sharing, input sample-and-hold amplifier cancellation, and dynamic comparator used to reduce the power. Technology non-idealities were included in a transistor-level Monte-Carlo simulation of the ADC. Simulation results show that a free dynamic range of 82dB is achieved for an input of 1MHz at a full speed of 10MHz while consuming only 11mW of power in the analog section.