This article describes a four-level pulse amplitude modulation (PAM-4) receiver with an analog front end (AFE) and a 12-tap direct decision feedback equalizer (DFE). A 1.5-stage slicer is proposed and the layout arrangement is optimized to relax the stringent timing constraint of the first tap loop. The post simulation results show that, compared with the traditional strong-arm slicer, the proposed 1.5-stage slicer reduces the clock-to-Q delay by 18%, which allows the implementation of the receiver with energy efficiency of 4.2 pJ/bit at 40 Gbps and a core area of 0.27 mm 2 in 65-nm CMOS process.