This letter presents a sub-6-GHz 100-Mb/s receiver that employs a fully balanced FSK, namely, a binary frequency-domain OOK (BFOOK) modulation. Demodulation is done based on a delay-line FM demodulator and a sideband energy detection (SB-ED) circuit with reduced noise bandwidth by leveraging a fully balanced BFOOK feature. A prototype 3.5-GHz receiver based on the proposed architecture is implemented in 65-nm CMOS. The receiver performs 100-Mb/s BFOOK demodulation and consumes 24.3 mW with the sensitivity of -62 dBm, achieving high energy efficiency of 243 pJ/b.