Different from the conventional two-point modulation (TPM) type-II phase-locked loops (PLLs) requiring non-trivial gain calibrations and TPM type-III PLLs with loop stability concern and limited chirp rate, a self-adapting gain mismatch TPM type-II digital PLL is proposed in this article. It directly detects frequency error as its input signal, allowing frequency ramp tracking with zero steady-state frequency error using a type-II PLL. In addition, the maximum trackable slope in the case of the proposed TPM type-II PLL is intrinsically larger than that of the conventional TPM type-III PLL. A polarity navigator is embedded in the digital loop filter to improve the linearity at the chirp turning-around points (TAPs). Fabricated in a 28-nm complementary metal-oxide-semiconductor (CMOS) technology, the proposed PLL consumes 23 mW from a 1-V power supply and occupies 0.31 mm2. The measurement results indicate that the proposed PLL can generate a precise triangular chirp with 2.27-GHz bandwidth (BW) and 18.2-μs period at 12.5 GHz. To the best knowledge of the authors, this work demonstrates the widest normalized Chirp-bandwidth and the fastest chirp rate simultaneously.