This paper presents a power efficient 12-bit successive aproximation register analog-to-digital converter (SAR ADC) operated at a supply voltage of 0.6V. A binary-scaled redundant technology for SAR ADC is proposed based on split-capacitor DAC architecture. It suppresses the decision error without sacrificing the resolution. In addition, a feedback controlled bias technique is applied to the comparator reducing the power consumption for comparison by 21.6%. The proposed ADC was fabricated in 0.18渭m CMOS technology, occupiing an core area of 0.07mm2. The measured DNL and INL is +0.46/鈭?.50 LSB and +0.98/鈭?.95 LSB, respectively. A SINAD of 68.1dB and SFDR of 83.0dB are achieved, respectively, while operating at a sampling rate of 100kS/s. The power consuming of the proposed ADC is 1.35uW, resulting in an FOM of 6.5fJ/Conversion-step.