A full-customized standard cell library using thick-gate transistors in TSMC 65nm technology is proposed for low static power demand in long-term monitoring IoT systems. The transistors are working in near/sub-threshold region, and channel length are increased for drain-induced barrier lowering (DIBL) effect inhibition. The standard cell layout area is optimized using dynamic N-well (NW) height. Algorithms are proposed for automatically DRC violations fixing due to cancellation of fillers. The customized standard cell library stands out for >400x smaller leakage power consumption compared to commercial library.