This Letter presents a digital low-dropout regulator (LDO) that achieves fast transient response with a flash ADC-based parallel comparison. A non-linear decoder is employed in the flash ADC to further enhance the transient response. In the design of the power switch array, an exponential-ratio array (ERA) is adopted for high load driving capacity. The proposed digital LDO implemented in 65-nm CMOS achieves a load range of 0.04-82.7 mA when the input voltage and the output voltage are 1.0 and 0.9 V, respectively. The digital LDO achieves a settling time of 6 渭s with a load step of 48 mA, exhibiting the state-of-the-art normalised settling time for the clock frequency of 1 MHz.