A 1.25-8.5 Gb/s wide range clock and data recovery (CDR) circuit in a multi-protocol SerDes is presented in this paper. The CDR is based on phase interpolator (PI). The local off-chip reference clock is interpolated by the PI to recover the clock at the same frequency as the data rate. Then CDR could retime received data with input jitter and noise in order to export clean waveforms. The circuit is designed in 40nm CMOS technology at 1.1 V supply voltage. Measured results show that bit error rate (BER) is less than 1e-9 and jitter tolerance (JTOL) agrees with template requirements at 1.25-8.5 Gb/s.