This paper describes a calibration-free two-point modulation method for spread-spectrum clock generators (SSCGs) by utilizing a two-stage nested-loop BBPLL architecture. Having a 1-bit TDC and an absolute-gain DCO, the two-point modulation based on the nested-loop BBPLL does not suffer from nonlinearity of the TDC and the DCO. A prototype 5GHz SSCG is implemented in 65nm CMOS. The proposed SSCG achieves a clock power reduction of 26dB with 200kHz modulation frequency and 5000ppm frequency spread, consuming 9mW with 1V supply.