An ultra-low power 12-bit successive-approximation-register (SAR)ADC was designed for implantable electrocardiography (ECG)monitoring.In order to meet the requirements of low power consumption,a timedivision comparison scheme with static pre-amplification comparators and dynamic pre-amplification comparators working at different timing was proposed.Low power was achieved on the basis of satisfying the comparison accuracy by the proposed scheme.In addition,the techniques such as asynchronous self-controlled logic operating, dual-voltage power supplying and transistors minimum gate length stacking were utilized to reduce the leakage current.This ADC was implemented in a 65nm CMOS process.The simulation results showed that,at a sampling rate of I kS/s,the SNDR was more than 69.9dB at different corners,the corresponding effective number of bit (ENOB)was 11.3bit,and the power consumption was only 30nW.The leakage consumption occupied 11%of the total power consumption.Thus the figure-of-merit (FoM)was 11.8fJ/(conv ·step).