This brief describes a high-speed auto-calibrated bit slicer for energy and envelope detection receivers. For robust bit decision, a digital-assisted calibration method with auto threshold estimation and auto phase acquisition is employed. The bit slicer consists of a phase-locked loop for multi-phase clock generation and a dynamic comparator in which the bulk voltage of the input transistor is trimmed for threshold voltage control. The proposed bit slicer is implemented in 65-nm 1P9M CMOS, occupying a total area of 0.07 mm2. Experimental results show that the bit slicer achieves a sensitivity of 6.1 mV at 1 GHz and consumes 1.6 mW from a 1-V supply.