This paper describes a fully integrated two-stage digital low-dropout regulator (DLDO) architecture for robust frequency generation under low supply voltage. The DLDO designed for a voltage-controlled oscillator (VCO) in the phase-locked loop (PLL) provides constant or temperature-compensated supply voltage with a 1-bit 螖危 modulated fine loop, while offering fast transient performance over load current jump with the multi-comparator coarse loop. The proposed DLDO designed in 65nm CMOS generates a noise-shaped output whose peak value is less than 1mV with a 200pF on-chip capacitor. The low dropout voltage of 50mV from a 1.0V supply is achieved with the load current ranging from 2.0渭A to 13.0mA.