An integrated 21.4–22.4 GHz fractional-N phase-locked loop (PLL)-based frequency synthesizer with low phase noise LC voltage-controlled oscillator (VCO) is implemented for a RF receiver in wireless communication systems. The K-band VCO generates a signal with a phase noise that is lower than ?93.4 dBc/Hz at 1 MHz offset frequency, using a current source filtering technique to improve the phase noise while having a 11% tuning range. The VCO achieves a figure-of-merit (FOM) of ?179.5 dBc/Hz with a power consumption of 16 mW. The transient mismatch of the charging and discharging current in the charge pump is optimized about 0.1% in the typical case, which minimizes the steady-state phase error in the PLL. The PLL outputs a signal with a phase noise that is lower than ?97.5 dBc/Hz at 1 MHz offset frequency with a total power consumption of 53 mW in 90nm CMOS