This paper proposes an open-source based 32-bit digital signal processor (DSP) suitable for embedded multimedia processing applications. The DSP is a MIPS-based scalar RISC with Harvard micro architecture, 5-stage integer pipeline and enhanced multimedia-processing capacity. It features a data path including non-aligned data access mechanism, two-dimensional DMA function and separated embedded instruction and data memories. This special architecture greatly promotes execution efficiency of boundary-crossed and block data access operations often found in multimedia processing. The processor achieves 80-MIPS performance with typical power dissipation of 88 mW. The prototype has been fabricated using UMC 0.18mum n-well 1P6M standard CMOS technology